M68HC11 and M68HC12 Dependent Features
**************************************

M68HC11 and M68HC12 Options
===========================

The Motorola 68HC11 and 68HC12 version of AS has a few machine dependent options.

This option switches the assembler in the M68HC11 mode. In this mode, the assembler only accepts 68HC11 operands and mnemonics. It produces code for the 68HC11.

This option switches the assembler in the M68HC12 mode. In this mode, the assembler also accepts 68HC12 operands and mnemonics. It produces code for the 68HC12. A fiew 68HC11 instructions are replaced by some 68HC12 instructions as recommended by Motorola specifications.

You can use the --strict-direct-mode option to disable the automatic translation of direct page mode addressing into extended mode when the instruction does not support direct mode. For example, the clr instruction does not support direct page mode addressing. When it is used with the direct page mode, AS will ignore it and generate an absolute addressing. This option prevents AS from doing this, and the wrong usage of the direct page mode will raise an error.

The --short-branchs option turns off the translation of relative branches into absolute branches when the branch offset is out of range. By default AS transforms the relative branch (bsr, bgt, bge, beq, bne, ble, blt, bhi, bcc, bls, bcs, bmi, bvs, bvs, bra) into an absolute branch when the offset is out of the -128 .. 127 range. In that case, the bsr instruction is translated into a jsr, the bra instruction is translated into a jmp and the conditional branchs instructions are inverted and followed by a jmp. This option disables these translations and AS will generate an error if a relative branch is out of range. This option does not affect the optimization associated to the jbra, jbsr and jbXX pseudo opcodes.

The --force-long-branchs option forces the translation of relative branches into absolute branches. This option does not affect the optimization associated to the jbra, jbsr and jbXX pseudo opcodes.

You can use the --print-insn-syntax option to obtain the syntax description of the instruction when an error is detected.

The --print-opcodes option prints the list of all the instructions with their syntax. The first item of each line represents the instruction name and the rest of the line indicates the possible operands for that instruction. The list is printed in alphabetical order. Once the list is printed AS exits.

The --generate-example option is similar to --print-opcodes but it generates an example for each instruction instead.

Syntax
======

In the M68HC11 syntax, the instruction name comes first and it may be followed by one or several operands (up to three). Operands are separated by comma (,). In the normal mode, AS will complain if too many operands are specified for a given instruction. In the MRI mode (turned on with -M option), it will treat them as comments. Example:

     inx
     lda  #23
     bset 2,x #4
     brclr *bot #8 foo

The following addressing modes are understood:

Immediate
     #NUMBER

Address Register
     NUMBER,X, NUMBER,Y

     The NUMBER may be omitted in which case 0 is assumed.

Direct Addressing mode
     *SYMBOL, or *DIGITS

Absolute
     SYMBOL, or DIGITS

Floating Point
==============

Packed decimal (P) format floating literals are not supported. Feel free to add the code!

The floating point formats generated by directives are these.

.float
     Single precision floating point constants.

.double
     Double precision floating point constants.

.extend
.ldouble
     Extended precision (long double) floating point constants.

Opcodes
=======

Branch Improvement
------------------

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by prepending j to the start of Motorola mnemonic. These pseudo opcodes are not affected by the --short-branchs or --force-long-branchs options.

The following table summarizes the pseudo-operations.

                                   Displacement Width
               +-------------------------------------------------------------+
               |                     Options                                 |
               |    --short-branchs            --force-long-branchs          |
               +--------------------------+----------------------------------+
     Pseudo-Op |BYTE             WORD     | BYTE          WORD               |
               +--------------------------+----------------------------------+
           bsr | bsr <pc-rel>    <error>  |               jsr <abs>          |
           bra | bra <pc-rel>    <error>  |               jmp <abs>          |
          jbsr | bsr <pc-rel>   jsr <abs> | bsr <pc-rel>  jsr <abs>          |
          jbra | bra <pc-rel>   jmp <abs> | bra <pc-rel>  jmp <abs>          |
           bXX | bXX <pc-rel>    <error>  |               bNX +3; jmp <abs>  |
          jbXX | bXX <pc-rel>   bNX +3;   | bXX <pc-rel>  bNX +3; jmp <abs>  |
               |                jmp <abs> |                                  |
               +--------------------------+----------------------------------+
     XX: condition
     NX: negative of condition XX

jbsr
jbra
     These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target.

jbXX
     Here, jbXX stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test.  The full list of pseudo-ops in this family is:

           jbcc   jbeq   jbge   jbgt   jbhi   jbvs   jbpl  jblo
           jbcs   jbne   jblt   jble   jbls   jbvc   jbmi

     For the cases of non-PC relative displacements and long displacements, AS issues a longer code fragment in terms of NX, the opposite condition to XX.  For example, for the non-PC relative case:

              jbXX foo

     gives

               bNXs oof
               jmp foo
           oof: