Subject: Re: Synertek 6507

From: "Dwight K. Elvey" <[email-masked]>
Date: Wed Mar 12 18:53:00 2003

>From: "Jim Kearney" <[email-masked]>
>
>>From: "Dwight K. Elvey" <[email-masked]>
>>  I'm looking for a data sheet for the Synertek 6507.
>> This is not the same as the reduced pin 6502's of the
>> same number by other manufactures. This is a video control
>> chip. If anyone has an old Synertek book with the
>> programming information for one of these I'd like
>> to get a photo copy??
>
>According to my 1983 Synertek book, the SY6507 _is_ a 28-pin 65xx CPU with
>8K addressing.  The only video controllers they list are the SY6545, SY6845,
>SY66450 and SY66550.
>

Hi Jim
 This is what Eric Smith tells me as well. As I told
him, it doesn't make much sense. The board has a 6502
as well as the 6507 with the data lines tied together.
I guess they could use opposite phases or something.
I was tracing down the sync signals for the video
and they seem to be coming from this part??
I do have a schematic someplace but I haven't located
it yet.
 Now I have a mystery to solve?
Dwight

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From: "Jim Kearney" <[email-masked]>
Date: Wed Mar 12 19:27:00 2003

>  Now I have a mystery to solve?

Possibly it's a variation of the Lancaster TVT (Cheap Video) design?

What is it?

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From: "Hans Franke" <[email-masked]>
Date: Thu Mar 13 03:45:00 2003

> and they seem to be coming from this part??

Now it would be interesting where they go. Maybe the
6507 CPU get's an interupt every line, or screen ?

>  Now I have a mystery to solve?

That's all what classic computing or computing in
general is about.

Gruss
H.

--
VCF Europa 4.0 am 03./04. Mai 2003 in Muenchen
http://www.vcfe.org/

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From: [email-masked] (Tony Duell)
Date: Thu Mar 13 19:25:00 2003

>  This is what Eric Smith tells me as well. As I told

And it's waht I suspect too...

> I guess they could use opposite phases or something.

Indeed. That was a very common trick to have 2 650x CPUs in parallel. 
It's how the CBM IEEE-488 disk drives were designed, for example. You 
need a mux on the address lines (because the CPU does not tri-state those 
between memory accesses), but you can tie the data lines together.

> and they seem to be coming from this part??

Think of the 6507 as (very) programmable counter chain (in the simplest 
case just have it executing NOPs and JMPs). That's the video address 
logic. And you could probably get it to pulse the high-order address 
lines (by jumping up there and back again) to generate sync signals.

I once had this idea (which I've never followed up) to use a common, 
fast, 8 bit processor with no instruction pipelining (so you know what 
the buses are doing and when) as a microcode sequencer. Just give it 8+n 
bit wide memory, with the 8 bits consisting of NOPs and (conditional) 
jumps. the n bits are the control lines to whatever you're microcoding. 

-tony

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From: "Eric Smith" <[email-masked]>
Date: Thu Mar 13 21:40:01 2003

Tony wrote:
> case just have it executing NOPs and JMPs).

Typically you want some instruction other than NOP.  For instance,
using LDA immediate lets you fetch consecutive addresses on every
cycle.

> jumps. the n bits are the control lines to whatever you're microcoding.

Back in 1993 or so, I was thinking about using an AMD 29005 RISC
microprocessor as a microprogram sequencer for a 36-bit computer.
But the 29005 doesn't qualify as common.